Method of forming contact included in semiconductor device

ABSTRACT

A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl 4  and H 2  onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.

CROSS-REFERENCE TO THE RELATED APPLICATION

This application claims priority from Korean Patent Application No.10-2021-0084676, filed on Jun. 29, 2021, in the Korean IntellectualProperty Office, the disclosure of which is incorporated herein byreference in its entirety.

BACKGROUND 1. Field

The example embodiments of the disclosure relate to a method of forminga contact included in a semiconductor device and/or electronic device.

2. Description of the Related Art

Research on technologies for controlling a resistance-capacitance delay(RC delay) of a DRAM device is being conducted. The RC delay timerequired in a DRAM device may be varied in accordance with aconfiguration of the DRAM device. To this end, technology capable offinely adjusting RC delay is needed.

SUMMARY

The example embodiments of the disclosure provide a method for adjustinga thickness of a dielectric layer formed together with a contact uponformation of the contact.

A method of forming a contact in accordance with an example embodimentof the disclosure may include providing a semiconductor substrateincluding a silicon oxide film to an interior of a chamber; subjecting asurface of the silicon oxide film to plasma nitrification treatment;supplying a source gas including TiCl₄ and H₂ onto the silicon oxidefilm subjected to the plasma nitrification treatment; and forming abarrier Lanier by igniting a plasma using the source gas.

A method of forming a contact in accordance with an example embodimentof the disclosure may include forming an interlayer insulating layer ona semiconductor substrate, the semiconductor substrate including atransistor; forming a contact hole by etching the interlayer insulatinglayer; subjecting the interlayer insulating layer to plasmanitrification treatment; supplying a source gas including TiCl₄ and H₂onto the interlayer insulating layer subjected to the plasmanitrification treatment; forming a barrier lay by igniting a plasmausing the source gas; and forming a metal layer on the barrier layer.

A method of forming a contact in accordance with an example embodimentof the disclosure may include forming an interlayer insulating layer ona semiconductor substrate, the semiconductor substrate including atransistor; forming a contact hole by etching the interlayer insulatinglayer; forming a TiO₂ layer on the interlayer insulating layer bysupplying a source gas including TiCl₄ and H₂ onto the interlayerinsulating layer; forming a barrier layer by igniting a plasma using thesource gas; and forming a metal layer on the barrier layer. The formingthe TiO₂ layer may include adjusting a thickness of the TiO₂ layer byadjusting a partial pressure of the TiCl₄ to a level and maintaining thelevel.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flowchart of a method of forming a dielectric layer and abarrier layer on a silicon oxide film in accordance with some exampleembodiments.

FIGS. 2A and 2B are concept views schematically shown to explain themethod of FIG. 1 .

FIG. 3 is a flowchart of a method for forming a dielectric layer and abarrier layer on a silicon oxide film in accordance with some exampleembodiments.

FIGS. 4A, 4B, 4C, and 4D are concept views schematically shown toexplain the method of FIG. 3 .

FIG. 5 is a flowchart explaining a method for forming a contact of asemiconductor device in accordance with some example embodiments.

FIGS. 6 to 11 are sectional views explaining the method of FIG. 5 .

FIG. 12 is a flowchart explaining a method for forming a contact of asemiconductor device in accordance with some example embodiments.

FIG. 13 is a schematic plan view of a semiconductor device including acontact according to some example embodiments.

FIG. 14 is a cross-sectional view taken along line I-I′ in FIG. 13 .

FIGS. 15 and 16 are enlarged views of a portion P1 of FIG. 14 .

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

When the terms “about” or “substantially” are used in this specificationin connection with a numerical value, it is intended that the associatednumerical value includes a manufacturing tolerance (e.g., ±10%) aroundthe stated numerical value. Further, regardless of whether numericalvalues or shapes are modified as “about” or “substantially,” it will beunderstood that these values and shapes should be construed as includinga manufacturing or operational tolerance (e.g., ±10%) around the statednumerical values or shapes.

FIG. 1 is a flowchart of a method of forming a dielectric layer and abarrier layer on a silicon oxide film in accordance with some exampleembodiments. FIGS. 2A and 2B are concept views schematically shown toexplain the method of FIG. 1 .

Referring to FIGS. 1, 2A and 2B, the method may include providing asemiconductor substrate including a silicon oxide (e.g., SiO₂) film 200to an interior of a chamber (S10), and performing a plasma enhancedchemical vapor deposition (PECVD) process on the silicon oxide film 200(S20). Though the semiconductor substrate is illustrated as includingsilicon oxide, in some example embodiments, the semiconductor substratemay include other oxides. For example, the oxide may be an insulatingoxide of the semiconductor included in semiconductor substrate.

The PECVD process S20 may include supplying TiCl₄ and H₂, which aresource gases, to an interior of the chamber (S21), and igniting aplasma, thereby forming a barrier layer 204 (S22). In some exampleembodiments, the supply of TiCl₄ and H₂, which are source gases, to theinterior of the chamber may include forming a dielectric layer 202 onthe silicon oxide film 200. For example, before forming the barrierlayer 204 (which may be a Ti layer) the source gases (e.g., TiCl₄ andH₂) may be supplied to the interior of the chamber (e.g., before plasmaignition). The PECVD process S20 may be performed at about 400° C. ormore. When the source gases, are supplied to the interior of thechamber, which is maintained at 400° C. or more, TiCl₄ and H₂ may reactwith the silicon oxide film 200 and, as such, a TiO₂ layer (e.g., thedielectric layer 202) may be formed on the silicon oxide film 200 inaccordance with Reaction Formula 1 as follows:

2Si—OH+TiCl₄→2Si—Cl+TiO₂+2HCl[Reaction Formula 1]

In these cases, the thickness of the formed TiO₂ layer may be varied inaccordance with a partial pressure of TiCl₄ supplied to the interior ofthe chamber. For example, the thickness of the TiO₂ layer may be thinwhen the partial pressure of TiCl₄ supplied to the interior of thechamber is low and constant. As variations in the partial pressure ofTiCl₄ supplied to the interior of the chamber increases, and the partialpressure of TiCl₄ increases, the resulting TiO₂ layer may be formed tobe thicker.

When a TiO₂ layer, which is a high dielectric material, is formed to athickness not smaller than a determined (or alternatively apredetermined) thickness upon formation of a contact used in asemiconductor device, resistance-capacitance (RC) delay of the resultantsemiconductor device may become excessively greater than a required(and/or otherwise determined) value. As a result, there may be a problemin reliability of the semiconductor device. To this end, the partialpressure of TiCl₄ supplied upon supply of the source gases may beadjusted to a determined (or alternatively a predetermined) level and,as such, the thickness of the TiO₂ layer may be adjusted to a desiredthickness. In accordance with adjustment of the partial pressure ofTiCl₄, it may be possible to adjust the thickness of the TiO₂ layerwithin about 3 Å to 6 Å. For example, in order to form the TiO₂ layer tohave a thickness of about 3 Å to 6 Å, the partial pressure of TiCl₄ maybe adjusted such that the partial pressure ratio TiCl₄/H₂ of TiCl₄ andH₂ is in a range of 1/750 to 1/250.

After the TiO₂ layer (e.g., the dielectric layer 202) is formed on thesilicon oxide film 200, and as TiCl₄ and H₂, which are source gases, arebeing supplied to the interior of the chamber, a plasma may be formedthrough plasma ignition of the residual TiCl₄ not taking part in thereaction forming the TiO₂ layer. As the plasma is formed using thesource gases (e.g., TiCl₄ and H₂) a Ti layer (e.g., the barrier layer204) may be deposited on TiO₂.

FIG. 3 is a flowchart of a method for forming a dielectric layer and abarrier layer on a silicon oxide film in accordance with some exampleembodiments. FIGS. 4A, 4B, 4C, and 4D are concept views schematicallyshown to explain the method of FIG. 3 .

Referring to FIG. 3 , the method may further include subjecting asurface of the silicon oxide film 200 (e.g., as described with referenceto FIGS. 1, 2A and 2B) to plasma nitrification treatment beforeexecution of the plasma enhanced chemical vapor deposition (PECVD)process on the silicon oxide film 200 (S15). The plasma nitrificationtreatment for the silicon oxide film 200 may be performed beforeexecution of the PECVD process (S20) (e.g., before the formation of thebarrier layer 204). In some example embodiments, for example, the plasmanitrification treatment of the silicon oxide film 200 may be performedbefore the source gases (e.g., TiCl₄ and H₂) are supplied to theinterior of the chamber (and/or before a TiO₂ layer is formed).

The plasma nitrification treatment for the surface of the silicon oxidefilm 200 may be induction of SiO₂—N coupling through mixture of thesilicon oxide film 200 and nitrogen. For example, the plasmanitrification treatment may be performed in a direct plasma manner at atemperature of 400° C. to 500° C. and a pressure of 4 to 6 Torr in anatmosphere containing NH₃, Ar, and H₂ as source gases in a reactionspace of the chamber.

After the surface of the silicon oxide film 200 is subjected to theplasma nitrification treatment (S15), the PECVD process described withreference to FIG. 1 may be performed (S20). For example, first, TiCl₄and H₂ may be supplied to the interior of the chamber (S21).

Although a TiO₂ layer, which is the dielectric layer 202, may be formedthrough reaction of TiCl₄ with the silicon oxide film 200, as describedabove, the reaction amount between the silicon oxide film 200 and TiCl₄may be reduced because the surface of the silicon oxide film 200 hasbeen subjected to the nitrification treatment. As shown in FIG. 4B, thenitrogen coupled to the surface of the silicon oxide film 200 mayfunction as a protective layer for the surface of the silicon oxide film200, thereby suppressing reaction between the silicon oxide film 200 andTiCl₄. As a result, the thickness of the formed TiO₂ layer may bereduced.

In some example embodiments, after the plasma nitrification treatment ofthe surface of the silicon oxide film 200, the partial pressures ofTiCl₄ and H₂ may be controlled to be determined (or alternatively apredetermined) levels while being constant, as described with referenceto FIG. 1 , and the resultant TiCl₄ and H₂ may be supplied to theinterior of the chamber. In these cases, when TiCl₄ and H₂ are suppliedunder the condition that the partial pressure ratio TiCl₄/H₂ of TiCl₄and H₂ is in a range of 1/750 to 1/250, the thickness of the TiO₂ layermay be adjusted to be in a range of about 0 to 2.5 Å. For example, whenthe partial pressure ratio of TiCl₄ and H₂ is adjusted after the plasmanitrification treatment, it may be possible to reduce the thickness ofthe TiO₂ layer to 2.5 Å or less and/or to completely prevent formationof TiO₂. As such, it may be possible to minimize RC delay by preventingformation of a TiO₂ layer and/or reducing the thickness of the TiO₂layer upon forming a contact of a semiconductor device.

In some example embodiments, after the plasma nitrification treatmentfor the surface of the silicon oxide film 200, TiCl₄ may be suppliedwithout adjustment of the partial pressure thereof. When TiCl₄ issupplied without adjustment of the partial pressure thereof, the partialpressure of TiCl₄ in the chamber may be varied without being constantduring a period from a time immediately after TiCl₄ is supplied to atime before plasma ignition occurs. Furthermore, the partial pressureratio TiCl₄/H₂ of TiCl₄ and H₂ may be between 1/250 to 1/750. Forexample, when the partial pressure of TiCl₄ is not adjusted, the partialpressure ratio TiCl₄/H₂ of TiCl₄ and H₂ supplied to the interior of thechamber may be 1/250 to 1/150. In these cases, the thickness of theformed TiO₂ may be about 3 to 8 Å.

Thereafter, plasma ignition may be performed for residual TiCl₄ and H₂,thereby depositing the barrier layer 204 (e.g., a Ti layer) on thedielectric layer 202 (e.g., a TiO₂ layer), and/or the silicon oxide film200 (S22).

Referring to FIGS. 4C and 4D, in some example embodiments, a siliconoxynitride (“SiON”) layer 201 may be further formed on the silicon oxidefilm 200 by plasma nitrification treatment. After the plasmanitrification treatment, a dielectric layer 202 (e.g., a TiO₂ layer) maybe formed on the SiON layer 201 by supplying TiCl₄ and H₂. Subsequently,a barrier layer 204 (e.g., a Ti layer) may be deposited through plasmaignition. In some example embodiments, when the dielectric layer 202 isnot formed, the barrier layer 204 may be deposited on the SiON layer201.

FIG. 5 is a flowchart explaining a method for forming a contact of asemiconductor device in accordance with some example embodiments. FIGS.6 to 11 are sectional views explaining the method of FIG. 5 .

Referring to FIGS. 5 to 9 , the method may include forming an interlayerinsulating layer 200 on a semiconductor substrate 100 (S100), forming acontact hole H (S200), performing plasma nitrification treatment (S300),supplying a source gas (S400), forming barrier layers 204 and 206(S500), and forming a metal layer 208 (S600).

Referring to FIGS. 5 and 6 , the interlayer insulating layer 200 may beformed by depositing an oxide (e.g., silicon oxide) on the semiconductorsubstrate 100 (S100). Although omitted from FIGS. 6 to 9 , forconvenience of description, the semiconductor substrate 100 may beprovided with a structure such as a transistor having impurity regionsas a source region and a drain region. A structure, such as a bit line,a bit line contact, a storage node contact, a landing pad, and/or acapacitor, which is electrically to the transistor, may be provided onthe semiconductor substrate 100. The interlayer insulating layer 200 maybe formed on the above-described structures.

A contact hole H, which exposes a lower conductive layer ST, may beformed by etching the interlayer insulating layer 200 (S200). Forexample, the lower conductive layer ST may be a source/drain contactconnected to a source/drain region of a transistor provided at thesemiconductor substrate 100, a wiring layer such as a bit line, and/or aplate electrode (and/or an upper electrode) included in a capacitor.

Plasma nitrification treatment may be performed on the interlayerinsulating layer 200 formed with the contact hole H (S300). The plasmanitrification treatment may be performed in the same manner as theplasma nitrification treatment described with reference to FIGS. 3 and4A. For example, nitrogen in a plasma state may be introduced to asurface of the interlayer insulating layer 200 (which may be, e.g., asilicon oxide film), and, as such, a SiO₂—N coupling may be induced. Insome example embodiments, the plasma nitrification treatment may beperformed in a direct plasma manner at a temperature of 400° C. to 500°C. and a pressure of 4 to 6 Torr in an atmosphere containing NH₃, Ar,and H₂ in a reaction space of the chamber.

Referring to FIGS. 5 and 7 , a source gas for a PECVD process (S20) maybe supplied in the chamber and/or onto the interlayer insulating layer200, the surface of which has been subjected to the plasma nitrificationtreatment. Supply of the source gas may be performed in the same manneras described with reference to FIG. 1 or 3 . For example, TiCl₄ and H₂may be supplied onto the interlayer insulating layer 200 subjected tothe plasma nitrification treatment, as source gases of the PECVDprocess. As TiCl₄ is supplied to the interior of the chamber beforeformation of a plasma, and the internal temperature of the chamber ismaintained at 400° C. or more, TiCl₄ may react with the interlayerinsulating layer 200, and, as such, a dielectric layer 202 (e.g., a TiO₂layer) may be formed.

In some example embodiments, when TiCl₄ and H₂ are supplied to theinterior of the chamber under the condition that the partial pressureratio TiCl₄/H₂ of TiCl₄ and H₂ is adjusted to be 1/750 to 1/250, afterthe plasma nitrification treatment for the surface of the interlayerinsulating layer 200, the TiO₂ layer, which is the dielectric layer 202,may be formed to have a thickness of 0 to 2.5 Å. For example, thedielectric layer 202 may not be formed or may be formed to have athickness exceeding 0 Å, but not more than 2.5 Å.

In some example embodiments, formation of the dielectric layer 202 maynot include adjusting the partial pressure of TiCl₄. When TiCl₄ issupplied without adjustment of the partial pressure thereof, the partialpressure of TiCl₄ in the chamber may be varied during a period from atime immediately after TiCl₄ is supplied to a time before plasmaignition occurs. Furthermore, the partial pressure ratio TiCl₄/H₂ ofTiCl₄ and H₂ may be between 1/750 to 1/250. For example, when thepartial pressure of TiCl₄ is not adjusted, the partial pressure ratioTiCl₄/H₂ of TiCl₄ and H₂ supplied to the interior of the chamber may be1/250 to 1/150. In these cases, the thickness of the formed TiO₂ may beabout 3 Å to 8 Å. As such, it may be possible to minimize RC delayoccurring due to a TiO₂ layer, which is included in a contact in asemiconductor device using the contact, by preventing formation of theTiO₂ layer and/or reducing the thickness of the TiO₂ layer.

Referring to FIGS. 5 and 8 , barrier layers 204 and 206 may be formed onthe dielectric layer 202. Formation of the barrier layers 204 and 206may include forming a first barrier layer 204, and forming a secondbarrier layer 206. Formation of the first barrier layer 204 may beperformed in the same manner as formation of the barrier layer 204described with reference to FIGS. 1 and 3 . A plasma may be formedthrough plasma ignition of residual TiCl₄ not taking part in reactionfor formation of the TiO₂ layer. As the plasma is formed using TiCl₄ andH₂ as source gases, a Ti layer, which may be at least one of barrierlayer 202 and/or 204, may be deposited on TiO₂. In some exampleembodiments, the dielectric layer 202 may be omitted, and the firstbarrier layer 204 may be directly formed on the interlayer insulatinglayer 200.

The second barrier layer 206 may be formed on the first barrier layer204, and the second barrier layer 206, which may be a TiN layer, may beformed through thermal chemical vapor deposition (CVD).

Referring to FIGS. 5 and 9 , a metal layer 208 may be formed on thebarrier layers 204 and 206. The metal layer 208, may be a W layer, maybe formed, e.g., through atomic layer deposition (ALD) and/or chemicalvapor deposition (CVD). Thereafter, node separation among contacts maybe performed through a chemical mechanical polishing (CMP) process.

Referring to FIGS. 5, 10, and 11 , in some example embodiments, an SiONlayer 201 may be further formed on the interlayer insulating layer 200through plasma nitrification treatment. Subsequently, a dielectric layer202, which is a TiO₂ layer, a first barrier layer 204, which is a Tilayer, a second barrier layer 206, which is a TiN layer, and a metallayer 208, which is a W layer, may be sequentially stacked on the SiONlayer 201 by performing the processes described with reference to FIGS.7 to 9 after the plasma nitrification treatment. In an embodiment, thedielectric layer 202, which is a TiO₂ layer, may not be formed. In thiscase, the first barrier layer 204, which is a Ti layer, may be directlyformed on the SiON layer 201.

FIG. 12 is a flowchart explaining a method for forming a contact of asemiconductor device in accordance with an exemplary embodiment of thedisclosure.

Referring to FIG. 12 , the method may omit the plasma nitrificationtreatment performed in the contact formation method described withreference to FIG. 5 . That is, the method may adjust the thickness of aTiO₂ layer, which is a dielectric layer 202, by supplying TiCl₄ onto aninterlayer insulating layer 200, which is silicon oxide, under thecondition that the partial pressure of TiCl₄ is adjusted. For example,the TiO₂ layer may be formed to have a thickness of about 3 to 6 Å byadjusting the partial pressure of TiCl₄ such that the partial pressureratio TiCl₄/H₂ of TiCl₄ and H₂ in a chamber is in a range of 1/750 to1/250.

FIG. 13 is a schematic plan view of a semiconductor device including acontact according to an exemplary embodiment of the disclosure. FIG. 14is a cross-sectional view taken along line I-I′ in FIG. 13 . Forconvenience of description, the plan view of FIG. 13 is shown in a statein which a contact is omitted. FIGS. 15 and 16 are enlarged views of aportion P1 of FIG. 14 .

Referring to FIGS. 13 and 14 , the semiconductor device may include asemiconductor substrate 100, a word line WL, a buffer layer 110, a bitline structure BLS, a direct contact DC, an insulating spacer 130, aburied contact BC, a landing pad LP, an insulating structure 140, a gatestructure GS, a contact plug 170, a first interlayer insulating layer165, a lower electrode 191, a supporter layer 192, a capacitordielectric layer 193, an upper electrode 194, a second interlayerinsulating layer 200, -contacts 201 c 1/201 c 2, and a wiring layer 220.

The semiconductor substrate 100 may include a cell area CELL and aperipheral circuit area PERI. The cell area CELL may be an area in whicha memory cell of a DRAM device is disposed, and the peripheral circuitarea PERI may be a core/peri area. The semiconductor substrate 100 mayinclude a semiconductor material. For example, the semiconductorsubstrate 100 may be and/or include a silicon substrate, a germaniumsubstrate, a silicon germanium substrate, a silicon-on-insulator (SOI)substrate, and/or the like.

The semiconductor substrate 100 may include a first active region AR1, asecond active region AR2, and an element isolation layer 105. Theelement isolation layer 105 may be an insulating layer buried in thesemiconductor substrate 100, and may define first active regions AR1 inthe cell area CELL. The first active region AR1 may have the form of anisland surrounded by the element isolation layer 105. The first activeregions AR1 may have the form of bars having a shorter axis and a longeraxis while being spaced apart from one another. The element isolationlayer 105 may define the second active region AR2 in the peripheralcircuit area PERI. The element isolation layer 105 may distinguish thecell area CELL and the peripheral circuit area PERI from each other.

Word lines WL may be disposed in parallel while being spaced apart fromone another in a first direction D1, and each of the word lines WL mayextend in a second direction D2 perpendicularly intersecting the firstdirection D1. The first direction D1 and the second direction D2 mayperpendicularly intersect each other on a plane parallel to a topsurface of the semiconductor substrate 100. The word lines WL mayintersect the first active regions AR1. For example, two word lines WLmay intersect one first active region AR1. The word lines WL may beburied in the semiconductor substrate 100.

The buffer layer 110 may be disposed between the semiconductor substrate100 and the bit line structure BLS. The buffer layer 110 may cover aportion of the top surface of the semiconductor substrate 100 and aportion of a top surface of the element isolation layer 105. Forexample, the buffer layer 110 may include silicon nitride.

Bit line structures BLS may extend in the first direction D1 while beingdisposed in parallel and spaced apart from one another in the seconddirection D2. The bit line structure BLS may include a conductive layer121, a first capping layer 122, an insulating liner 123 and a secondcapping layer 124 which are sequentially stacked on the buffer layer110. Although the conductive layer 121 is shown as being a single layer,for convenience of description, the conductive layer 121 may includemultiple layers. The first capping layer 122 may be disposed on theconductive layer 121, and the conductive layer 121 and the first cappinglayer 122 may have the same width in the second direction D2. Theinsulating liner 123 may cover the first capping layer 122 in the cellarea CELL, and may extend to the peripheral circuit area PERI. Thesecond capping layer 124 may cover at least a portion of the insulatingliner 123. The second capping layer 124 may extend to the peripheralcircuit area PERI. The conductive layer 121 may include, e.g., at leastone of polysilicon, TiN, TiSiN, W, tungsten silicide, and/or the like.Each of the first capping layer 122, the insulating liner 123, and thesecond capping layer 124 may include, e.g., at least one of siliconoxide, silicon nitride, silicon oxynitride, and/or the like.

The direct contact DC may be disposed at a lower portion of the bit linestructure BLS in a region where the bit line structure BLS contacts thefirst active region AR1. For example, the direct contact DC may fill aportion of a recess formed at the top surface of the substrate 100. Whenviewed in a top (and/or plan) view, the direct contact DC may overlapwith a central portion of the first active region AR1. The directcontact DC may electrically interconnect the first active region AR1 andthe bit line structure BLS. For example, the direct contact DC mayinclude a conductive material, e.g., polysilicon.

Insulating spacers 130 may be disposed at opposite side surfaces of thebit line structures BLS, respectively, and may extend alongcorresponding ones of the bit line structure BLS in the first directionD1, respectively. A portion of the insulating spacer 130 may extend intothe recess of the semiconductor substrate 100, and may cover a sidesurface of the direct contact DC. The insulating spacers 130 may includea single layer and/or multiple layers and may comprise an insulatingmaterial.

The buried contact BC may be disposed among the bit line structures BLS.The buried contact BC may be disposed among the insulating spacers 130.A lower portion of the buried contact BC may extend into thesemiconductor substrate 100 and, as such, may contact the first activeregion AR1. For example, the buried contact BC may include a conductivematerial, e.g., polysilicon.

The landing pad LP may be connected to an upper end of the buriedcontact BC, and a portion of the land pad LP may be disposed on the bitline structure BLS. The landing pad LP may be electrically connected tothe first active region AR1 via the buried contact BC. Insulatingstructures 140 may be disposed among landing pads LP. The insulatingstructures 140 may electrically insulate the landing pads LP from oneanother. Top surfaces of the insulating structures 140 may be coplanarwith a top surface of the landing pad LP. For example, the landing padLP may include a conductive material, e.g., tungsten, and the insulatingstructure 140 may include an insulating material, e.g., silicon oxide.

The gate structure GS may be disposed on the second active region AR2 inthe peripheral circuit area PERI. A source/drain region S/D may bedisposed at a top surface of the second active region AR2 adjacent tothe gate structure GS. The gate structure GS may include a gatedielectric layer 151, a gate electrode 152, and a gate capping layer 153which are sequentially stacked on the second active region AR2. Althoughthe gate electrode 152 is shown as being a single layer, the gateelectrode 152 may include multiple layers, and may include the samematerial as the conductive layer 121 of the bit line structure BLS.

Gate spacers 160 may be disposed on side walls of the gate structure GS.When viewed in a plan view, the gate spacer 160 may surround the gatestructure GS. The gate spacer 160 and the gate structure GS may becovered by the insulating liner 123 extending from the cell area CELL.The gate spacer 160 may include an insulating material, e.g., siliconoxide, silicon nitride, silicon oxynitride, and/or a combinationthereof.

The first interlayer insulating layer 165 may be disposed on theinsulating liner 123 in the cell area CELL and the peripheral circuitarea PERI. The first interlayer insulating layer 165 may be disposedunder the second capping layer 124. The interlayer insulating layer 165may be disposed on a side surface of the gate spacer 160. The firstinterlayer insulating layer 165 may include an insulating material,e.g., silicon oxide, silicon nitride, silicon oxynitride, and/or acombination thereof.

In the peripheral circuit area PERI, the contact plug 170 may bedisposed adjacent to the gate structure GS. The contact plug 170 mayextend through the first interlayer insulating layer 165 and the secondcapping layer 124 and, as such, may contact the second active regionAR2. A top surface of the contact plug 170 may be disposed at the samelevel as the top surface of the landing pad LP. The contact plug 170 mayinclude the same material as the landing pad LP. Upper portions ofcontact plugs 170 may have the form of lines extending in a horizontaldirection or islands spaced apart from one another. The insulatingstructures 140 may electrically insulate the contact plugs 170.

An etch stop layer 180 may be disposed on the landing pad LP, theinsulating structure 140, and the contact pug 170. For example, the etchstop layer 180 may include an insulating material, e.g., siliconnitride. The etch stop layer 180 may have etch selectivity, for example,compared to the insulating structure 140.

A capacitor structure may be disposed on the landing pad LP in the cellarea CELL. The capacitor structure may include a lower electrode 191, asupporter layer 192, a capacitor dielectric layer 193, and an upperelectrode 194. Lower electrodes 191 may extend through the etch stoplayer 180 and, as such, may be connected to corresponding ones of thelanding pads LP, respectively. The lower electrode 191 may have acylindrical shape, a cup shape, a pillar shape, and/or a hybrid shape(e.g., including both the cylindrical shape and the pillar shape). Thelower electrode 191 may include, e.g., a conductive materials such as ametal (e.g., Ti, W, Ni and/or Co) and/or a metal nitride (e.g., TiN,TiSiN, TiAlN, TaN, TaSiN, WN, etc.). The supporter layer 192 may beconnected to portions of side surfaces of the lower electrodes 191 and,as such, may prevent (and/or mitigate the potential for) a collapse ofthe lower electrodes 191. The supporter layer 192 may include aninsulating material, e.g., silicon nitride.

The capacitor dielectric layer 193 may be conformally formed alongsurfaces of the lower electrode 191 and the supporter layer 192. Thecapacitor dielectric layer 193 may include and insulating material suchas a metal oxide (e.g., at least one of HfO₂, ZrO₂, Al₂O₃, La₂O₃, Ta₂O₃,and/or TiO₂), a dielectric material having a perovskite structure (e.g.,SrTiO₃(STO), BaTiO₃, lead-zirconium-titanate (“PZT”) and/orlead-lanthanum-zirconium-titanate (“PLZT”)), and/or a combinationthereof.

The upper electrode 194 may be disposed on the capacitor dielectriclayer 193 and, as such, may cover the lower electrode 191. The upperelectrode 194 may include a conductive material, and SiGe covering theconductive material. The conductive material may include, for example, ametal (such as Ti, W, Ni and Co) and/or a metal nitride) such as TiN,TiSiN, TiAlN, TaN, TaSiN, WN, etc.).

The second interlayer insulating layer 200 may be disposed on the etchstop layer 180 in the cell area CELL and the peripheral circuit areaPERI. The second interlayer insulating layer 200 may cover the upperelectrode 194. The second interlayer insulating layer 200 may include aninsulating material, e.g., silicon oxide.

The contacts 201 c 1/201 c 2 may be electrically connected to atransistor in the cell area CELL and/or the peripheral circuit areaPERI. The contacts 201 c 1/201 c 2 may include a first contact 201 c 1and a second contact 201 c 2. The first contact 201 c 1 may extendthrough the second interlayer insulating layer 200 in the cell area CELLand, as such, may be connected to the upper electrode 194. The secondcontact 201 c 2 may extend through the second interlayer insulatinglayer 200 and the etch stop layer 180 in the peripheral circuit areaPERI and, as such, may be connected to the contact plug 170. The firstcontact 201 c 1 and the second contact 201 c 2 may be made of the samematerial, and may have the same configuration.

Wiring layers 220 may be disposed on the second interlayer insulatinglayer 200 and respective contacts 201 c 1 and 201 c 2. Although notshown, a third contact may be electrically connected to the bit linestructure BLS. The third contact may be formed using the same materialas the first and second contacts 201 c 1 and 201 c 2, and may have thesame configuration as the first and second contacts 201 c 1 and 201 c 2.The contact 201 c 1/201 c 2 may be formed through any one of the contactformation methods described with reference to FIGS. 5 to 12 .

Referring to FIGS. 14 and 15 , the second contact 201 c 2 may include adielectric layer 202 being a TiO₂ layer, a first barrier layer 204(e.g., a Ti layer), a second barrier layer 206 (e.g., a TiN layer), anda metal layer 208 (e.g., a W layer) which are sequentially stacked on asecond interlayer insulating layer 200. Here, when plasma nitrificationtreatment and adjustment of the partial pressure of TiCl₄ are performedupon forming the contact 201 c 1/201 c 2, the thickness of thedielectric layer 202 may be 2.5 Å or less, and/or the dielectric layer202 may not be formed at all. When only the plasma nitrificationtreatment is performed without adjustment of the partial pressure ofTiCl₄, the dielectric layer 202 may be formed to have a thickness of 3to 8 Å. When adjustment of the partial pressure of TiCl₄ is performedwithout plasma nitrification treatment, the dielectric layer 202 may beformed to have a thickness of 3 to 6 Å.

Referring to FIG. 16 , in some example embodiments, the second contact201 c 2 may further include an SiON layer 201. The SiON layer 201 may beinterposed between the second interlayer insulating layer 200 and thedielectric layer 202.

In accordance with the example embodiments of the disclosure, thethickness of a dielectric layer formed by plasma enhanced chemical vapordeposition (PECVD) for formation of a barrier layer, upon forming acontact of a DRAM device, may be adjusted and, as such, it may bepossible to adjust RC delay of the DRAM device.

While the example embodiments of the disclosure have been described withreference to the accompanying drawings, it should be understood by thoseskilled in the art that various modifications may be made withoutdeparting from the scope of the disclosure and without changingessential features thereof. Therefore, the above-described embodimentsshould be considered in a descriptive sense only and not for purposes oflimitation.

What is claimed is:
 1. A method of forming a contact, the methodcomprising: providing a semiconductor substrate comprising a siliconoxide film to an interior of a chamber; subjecting a surface of thesilicon oxide film to plasma nitrification treatment; supplying a sourcegas including TiCl₄ and H₂ onto the silicon oxide film subjected to theplasma nitrification treatment; and forming a barrier layer by ignitinga plasma using the source gas.
 2. The method according to claim 1,wherein the plasma nitrification treatment is performed in a directplasma manner at a temperature of 400 to 500° C. and a pressure of 4 to6 Torr in an atmosphere containing NH₃, Ar, and H₂.
 3. The methodaccording to claim 2, wherein the supplying the source gas comprisesforming a TiO₂ layer on the silicon oxide film, and the TiO₂ layer isformed to have a thickness of 3 to 8 Å.
 4. The method according to claim1, wherein the supplying the source gas comprises forming a TiO₂ layeron the silicon oxide film, and includes adjusting a thickness of theTiO₂ layer by adjusting a partial pressure of the TiCl₄ to a level andmaintaining the level.
 5. The method according to claim 4, wherein apartial pressure ratio TiCl₄/H₂ of the source case is 1/750 to 1/250. 6.The method according to claim 5, wherein the TiO₂ layer is formed tohave a thickness of 0 to 2.5 Å.
 7. The method according to claim 1,wherein the plasma nitrification treatment comprises forming an SiONlayer on the silicon oxide film.
 8. The method according to claim 1,wherein the barrier layer comprises a Ti layer.
 9. The method accordingto claim 8, further comprising: forming a TiN layer on the Ti layer. 10.The method according to claim 9, wherein the forming the TiN layerincludes a thermal chemical vapor deposition (CVD) process.
 11. A methodof forming a contact, comprising: forming an interlayer insulating layeron a semiconductor substrate, the semiconductor substrate comprising atransistor; forming a contact hole by etching the interlayer insulatinglayer; subjecting the interlayer insulating layer to plasmanitrification treatment; supplying a source gas including TiCl₄ and H₂onto the interlayer insulating layer subjected to the plasmanitrification treatment; forming a barrier layer by igniting a plasmausing the source gas; and forming a metal layer on the barrier layer.12. The method according to claim 11, wherein the plasma nitrificationtreatment is performed in a direct plasma manner at a temperature of 400to 500° C. and a pressure of 4 to 6 Torr in an atmosphere containingNH₃, Ar, and H₂.
 13. The method according to claim 11, wherein thesupplying source gas comprises forming a TiO₂ layer on the insulatinglayer, and adjusting a thickness of the TiO₂ layer by adjusting apartial pressure of the TiCl₄ to a level and maintaining the level. 14.The method according to claim 13, wherein a partial pressure ratioTiCl₄/H₂ of the source gas is 1/750 to 1/250.
 15. The method accordingto claim 14, wherein the TiO₂ layer is formed to have a thickness of 0to 2.5 Å.
 16. The method according to claim 11, wherein the plasmanitrification treatment comprises forming an SiON layer on theinterlayer insulating layer.
 17. The method according to claim 16,wherein the supplying the source gas comprises forming a TiO₂ layer onthe SiON layer.
 18. A method of forming a contact, comprising: formingan interlayer insulating layer on a semiconductor substrate, thesemiconductor substrate comprising a transistor; forming a contact holeby etching the interlayer insulating layer; forming a TiO₂ layer on theinterlayer insulating layer by supplying a source gas including TiCl₄and H₂ onto the interlayer insulating layer; forming a barrier layer byigniting a plasma using the source gas; and forming a metal layer on thebarrier layer, wherein the forming the TiO₂ layer includes adjusting athickness of the TiO₂ by adjusting a partial pressure of the TiCl₄ to alevel and maintaining the level.
 19. The method according to claim 18,further comprising: subjecting a surface of the interlayer insulatinglayer to plasma nitrification treatment before the forming the TiO₂layer, wherein the plasma nitrification treatment is performed in adirect plasma manner at a temperature of 400 to 500° C. and a pressureof 4 to 6 Torr in an atmosphere containing NH₃, Ar, and H₂.
 20. Themethod according to claim 18, wherein a partial pressure ratio TiCl₄/H₂of the source gas is 1/750 to 1/250.